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cuda_wrappers	[ DIR ]	drwxr-xr-x
llvm_libc_wrappers	[ DIR ]	drwxr-xr-x
openmp_wrappers	[ DIR ]	drwxr-xr-x
ppc_wrappers	[ DIR ]	drwxr-xr-x
__clang_cuda_builtin_vars.h	4.78 KB	-rw-r--r--
__clang_cuda_cmath.h	18.06 KB	-rw-r--r--
__clang_cuda_complex_builtins....	9.36 KB	-rw-r--r--
__clang_cuda_device_functions....	56.68 KB	-rw-r--r--
__clang_cuda_intrinsics.h	29.93 KB	-rw-r--r--
__clang_cuda_libdevice_declare...	21.87 KB	-rw-r--r--
__clang_cuda_math.h	15.99 KB	-rw-r--r--
__clang_cuda_math_forward_decl...	8.27 KB	-rw-r--r--
__clang_cuda_runtime_wrapper.h	17.61 KB	-rw-r--r--
__clang_cuda_texture_intrinsic...	31.86 KB	-rw-r--r--
__clang_hip_cmath.h	26.34 KB	-rw-r--r--
__clang_hip_libdevice_declares...	19.87 KB	-rw-r--r--
__clang_hip_math.h	31.96 KB	-rw-r--r--
__clang_hip_runtime_wrapper.h	4.65 KB	-rw-r--r--
__clang_hip_stdlib.h	1.19 KB	-rw-r--r--
__stddef_max_align_t.h	857 B	-rw-r--r--
__wmmintrin_aes.h	5.15 KB	-rw-r--r--
__wmmintrin_pclmul.h	1.99 KB	-rw-r--r--
adxintrin.h	7.37 KB	-rw-r--r--
altivec.h	697.32 KB	-rw-r--r--
ammintrin.h	7.54 KB	-rw-r--r--
amxcomplexintrin.h	6.81 KB	-rw-r--r--
amxfp16intrin.h	1.82 KB	-rw-r--r--
amxintrin.h	21.12 KB	-rw-r--r--
arm64intr.h	993 B	-rw-r--r--
arm_acle.h	25.66 KB	-rw-r--r--
arm_bf16.h	548 B	-rw-r--r--
arm_cde.h	32.67 KB	-rw-r--r--
arm_cmse.h	6.21 KB	-rw-r--r--
arm_fp16.h	16.92 KB	-rw-r--r--
arm_mve.h	1.48 MB	-rw-r--r--
arm_neon.h	2.45 MB	-rw-r--r--
arm_neon_sve_bridge.h	9.48 KB	-rw-r--r--
arm_sme_draft_spec_subject_to_...	60.2 KB	-rw-r--r--
arm_sve.h	1.51 MB	-rw-r--r--
armintr.h	843 B	-rw-r--r--
avx2intrin.h	186.96 KB	-rw-r--r--
avx512bf16intrin.h	10.51 KB	-rw-r--r--
avx512bitalgintrin.h	2.41 KB	-rw-r--r--
avx512bwintrin.h	75.33 KB	-rw-r--r--
avx512cdintrin.h	4.12 KB	-rw-r--r--
avx512dqintrin.h	58.75 KB	-rw-r--r--
avx512erintrin.h	11.83 KB	-rw-r--r--
avx512fintrin.h	382.64 KB	-rw-r--r--
avx512fp16intrin.h	156.63 KB	-rw-r--r--
avx512ifmaintrin.h	2.49 KB	-rw-r--r--
avx512ifmavlintrin.h	4.31 KB	-rw-r--r--
avx512pfintrin.h	4.53 KB	-rw-r--r--
avx512vbmi2intrin.h	13.17 KB	-rw-r--r--
avx512vbmiintrin.h	3.72 KB	-rw-r--r--
avx512vbmivlintrin.h	6.94 KB	-rw-r--r--
avx512vlbf16intrin.h	19.21 KB	-rw-r--r--
avx512vlbitalgintrin.h	4.23 KB	-rw-r--r--
avx512vlbwintrin.h	121.26 KB	-rw-r--r--
avx512vlcdintrin.h	7.66 KB	-rw-r--r--
avx512vldqintrin.h	46.41 KB	-rw-r--r--
avx512vlfp16intrin.h	85.51 KB	-rw-r--r--
avx512vlintrin.h	322.29 KB	-rw-r--r--
avx512vlvbmi2intrin.h	25.72 KB	-rw-r--r--
avx512vlvnniintrin.h	13.13 KB	-rw-r--r--
avx512vlvp2intersectintrin.h	4.44 KB	-rw-r--r--
avx512vnniintrin.h	4.21 KB	-rw-r--r--
avx512vp2intersectintrin.h	2.9 KB	-rw-r--r--
avx512vpopcntdqintrin.h	2 KB	-rw-r--r--
avx512vpopcntdqvlintrin.h	3.31 KB	-rw-r--r--
avxifmaintrin.h	5.75 KB	-rw-r--r--
avxintrin.h	195.41 KB	-rw-r--r--
avxneconvertintrin.h	14.09 KB	-rw-r--r--
avxvnniint16intrin.h	17.41 KB	-rw-r--r--
avxvnniint8intrin.h	18.67 KB	-rw-r--r--
avxvnniintrin.h	10.44 KB	-rw-r--r--
bmi2intrin.h	7.09 KB	-rw-r--r--
bmiintrin.h	14.12 KB	-rw-r--r--
builtins.h	741 B	-rw-r--r--
cet.h	1.49 KB	-rw-r--r--
cetintrin.h	3.27 KB	-rw-r--r--
cldemoteintrin.h	1.18 KB	-rw-r--r--
clflushoptintrin.h	1.17 KB	-rw-r--r--
clwbintrin.h	1.2 KB	-rw-r--r--
clzerointrin.h	1.19 KB	-rw-r--r--
cmpccxaddintrin.h	2.33 KB	-rw-r--r--
cpuid.h	11.01 KB	-rw-r--r--
crc32intrin.h	3.27 KB	-rw-r--r--
emmintrin.h	192.64 KB	-rw-r--r--
enqcmdintrin.h	2.12 KB	-rw-r--r--
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float.h	5.63 KB	-rw-r--r--
fma4intrin.h	6.82 KB	-rw-r--r--
fmaintrin.h	28.4 KB	-rw-r--r--
fxsrintrin.h	2.82 KB	-rw-r--r--
gfniintrin.h	7.57 KB	-rw-r--r--
hexagon_circ_brev_intrinsics.h	15.59 KB	-rw-r--r--
hexagon_protos.h	374.42 KB	-rw-r--r--
hexagon_types.h	130.33 KB	-rw-r--r--
hresetintrin.h	1.36 KB	-rw-r--r--
htmintrin.h	6.14 KB	-rw-r--r--
htmxlintrin.h	9.01 KB	-rw-r--r--
hvx_hexagon_protos.h	254.26 KB	-rw-r--r--
ia32intrin.h	12.72 KB	-rw-r--r--
immintrin.h	23.57 KB	-rw-r--r--
intrin.h	28.22 KB	-rw-r--r--
inttypes.h	2.26 KB	-rw-r--r--
invpcidintrin.h	764 B	-rw-r--r--
iso646.h	656 B	-rw-r--r--
keylockerintrin.h	17.98 KB	-rw-r--r--
larchintrin.h	7.8 KB	-rw-r--r--
limits.h	3.61 KB	-rw-r--r--
lwpintrin.h	5 KB	-rw-r--r--
lzcntintrin.h	3.18 KB	-rw-r--r--
mm3dnow.h	4.5 KB	-rw-r--r--
mm_malloc.h	1.88 KB	-rw-r--r--
mmintrin.h	55.98 KB	-rw-r--r--
module.modulemap	3.33 KB	-rw-r--r--
movdirintrin.h	1.57 KB	-rw-r--r--
msa.h	25.01 KB	-rw-r--r--
mwaitxintrin.h	2.19 KB	-rw-r--r--
nmmintrin.h	709 B	-rw-r--r--
opencl-c-base.h	30.38 KB	-rw-r--r--
opencl-c.h	874.39 KB	-rw-r--r--
pconfigintrin.h	1.19 KB	-rw-r--r--
pkuintrin.h	934 B	-rw-r--r--
pmmintrin.h	10.5 KB	-rw-r--r--
popcntintrin.h	1.82 KB	-rw-r--r--
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prfchwintrin.h	2.06 KB	-rw-r--r--
ptwriteintrin.h	1.05 KB	-rw-r--r--
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rdseedintrin.h	2.85 KB	-rw-r--r--
riscv_ntlh.h	855 B	-rw-r--r--
rtmintrin.h	1.25 KB	-rw-r--r--
s390intrin.h	604 B	-rw-r--r--
serializeintrin.h	881 B	-rw-r--r--
sgxintrin.h	1.77 KB	-rw-r--r--
sha512intrin.h	5.95 KB	-rw-r--r--
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sifive_vector.h	522 B	-rw-r--r--
sm3intrin.h	7.29 KB	-rw-r--r--
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stdalign.h	911 B	-rw-r--r--
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vpclmulqdqintrin.h	1.06 KB	-rw-r--r--
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wasm_simd128.h	76.25 KB	-rw-r--r--
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Code Editor : avx512vlvnniintrin.h

/*===------------- avx512vlvnniintrin.h - VNNI intrinsics ------------------===
 *
 *
 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 * See https://llvm.org/LICENSE.txt for license information.
 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 *
 *===-----------------------------------------------------------------------===
 */
#ifndef __IMMINTRIN_H
#error "Never use <avx512vlvnniintrin.h> directly; include <immintrin.h> instead."
#endif

#ifndef __AVX512VLVNNIINTRIN_H
#define __AVX512VLVNNIINTRIN_H

/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS128 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vnni"), __min_vector_width__(128)))
#define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vnni"), __min_vector_width__(256)))

/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with
/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed
/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
/// in \a S, and store the packed 32-bit results in DST.
///
/// This intrinsic corresponds to the <c> VPDPBUSD </c> instructions.
///
/// \code{.operation}
///    FOR j := 0 to 7
///      tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))
///      tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))
///      tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))
///      tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))
///      DST.dword[j] := S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
///    ENDFOR
///    DST[MAX:256] := 0
/// \endcode
#define _mm256_dpbusd_epi32(S, A, B) \
  ((__m256i)__builtin_ia32_vpdpbusd256((__v8si)(S), (__v8si)(A), (__v8si)(B)))

/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with
/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed
/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
/// in \a S using signed saturation, and store the packed 32-bit results in DST.
///
/// This intrinsic corresponds to the <c> VPDPBUSDS </c> instructions.
///
/// \code{.operation}
///    FOR j := 0 to 7
///      tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))
///      tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))
///      tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))
///      tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))
///      DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
///    ENDFOR
///    DST[MAX:256] := 0
/// \endcode
#define _mm256_dpbusds_epi32(S, A, B) \
  ((__m256i)__builtin_ia32_vpdpbusds256((__v8si)(S), (__v8si)(A), (__v8si)(B)))

/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with
/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit
/// results. Sum these 2 results with the corresponding 32-bit integer in \a S,
///  and store the packed 32-bit results in DST.
///
/// This intrinsic corresponds to the <c> VPDPWSSD </c> instructions.
///
/// \code{.operation}
///    FOR j := 0 to 7
///      tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])
///      tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])
///      DST.dword[j] := S.dword[j] + tmp1 + tmp2
///    ENDFOR
///    DST[MAX:256] := 0
/// \endcode
#define _mm256_dpwssd_epi32(S, A, B) \
  ((__m256i)__builtin_ia32_vpdpwssd256((__v8si)(S), (__v8si)(A), (__v8si)(B)))

/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with
/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit
/// results. Sum these 2 results with the corresponding 32-bit integer in \a S
/// using signed saturation, and store the packed 32-bit results in DST.
///
/// This intrinsic corresponds to the <c> VPDPWSSDS </c> instructions.
///
/// \code{.operation}
///    FOR j := 0 to 7
///      tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])
///      tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])
///      DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2)
///    ENDFOR
///    DST[MAX:256] := 0
/// \endcode
#define _mm256_dpwssds_epi32(S, A, B) \
  ((__m256i)__builtin_ia32_vpdpwssds256((__v8si)(S), (__v8si)(A), (__v8si)(B)))

/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with
/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed
/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
/// in \a S, and store the packed 32-bit results in DST.
///
/// This intrinsic corresponds to the <c> VPDPBUSD </c> instructions.
///
/// \code{.operation}
///    FOR j := 0 to 3
///      tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))
///      tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))
///      tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))
///      tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))
///      DST.dword[j] := S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4
///    ENDFOR
///    DST[MAX:128] := 0
/// \endcode
#define _mm_dpbusd_epi32(S, A, B) \
  ((__m128i)__builtin_ia32_vpdpbusd128((__v4si)(S), (__v4si)(A), (__v4si)(B)))

/// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with
/// corresponding signed 8-bit integers in \a B, producing 4 intermediate signed
/// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
/// in \a S using signed saturation, and store the packed 32-bit results in DST.
///
/// This intrinsic corresponds to the <c> VPDPBUSDS </c> instructions.
///
/// \code{.operation}
///    FOR j := 0 to 3
///      tmp1.word := Signed(ZeroExtend16(A.byte[4*j]) * SignExtend16(B.byte[4*j]))
///      tmp2.word := Signed(ZeroExtend16(A.byte[4*j+1]) * SignExtend16(B.byte[4*j+1]))
///      tmp3.word := Signed(ZeroExtend16(A.byte[4*j+2]) * SignExtend16(B.byte[4*j+2]))
///      tmp4.word := Signed(ZeroExtend16(A.byte[4*j+3]) * SignExtend16(B.byte[4*j+3]))
///      DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2 + tmp3 + tmp4)
///    ENDFOR
///    DST[MAX:128] := 0
/// \endcode
#define _mm_dpbusds_epi32(S, A, B) \
  ((__m128i)__builtin_ia32_vpdpbusds128((__v4si)(S), (__v4si)(A), (__v4si)(B)))

/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with
/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit
/// results. Sum these 2 results with the corresponding 32-bit integer in \a S,
/// and store the packed 32-bit results in DST.
///
/// This intrinsic corresponds to the <c> VPDPWSSD </c> instructions.
///
/// \code{.operation}
///    FOR j := 0 to 3
///      tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])
///      tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])
///      DST.dword[j] := S.dword[j] + tmp1 + tmp2
///    ENDFOR
///    DST[MAX:128] := 0
/// \endcode
#define _mm_dpwssd_epi32(S, A, B) \
  ((__m128i)__builtin_ia32_vpdpwssd128((__v4si)(S), (__v4si)(A), (__v4si)(B)))

/// Multiply groups of 2 adjacent pairs of signed 16-bit integers in \a A with
/// corresponding 16-bit integers in \a B, producing 2 intermediate signed 32-bit
/// results. Sum these 2 results with the corresponding 32-bit integer in \a S
/// using signed saturation, and store the packed 32-bit results in DST.
///
/// This intrinsic corresponds to the <c> VPDPWSSDS </c> instructions.
///
/// \code{.operation}
///    FOR j := 0 to 3
///      tmp1.dword := SignExtend32(A.word[2*j]) * SignExtend32(B.word[2*j])
///      tmp2.dword := SignExtend32(A.word[2*j+1]) * SignExtend32(B.word[2*j+1])
///      DST.dword[j] := Saturate32(S.dword[j] + tmp1 + tmp2)
///    ENDFOR
///    DST[MAX:128] := 0
/// \endcode
#define _mm_dpwssds_epi32(S, A, B) \
  ((__m128i)__builtin_ia32_vpdpwssds128((__v4si)(S), (__v4si)(A), (__v4si)(B)))

static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_dpbusd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
{
  return (__m256i)__builtin_ia32_selectd_256(__U,
                                     (__v8si)_mm256_dpbusd_epi32(__S, __A, __B),
                                     (__v8si)__S);
}

static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_dpbusd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
{
  return (__m256i)__builtin_ia32_selectd_256(__U,
                                     (__v8si)_mm256_dpbusd_epi32(__S, __A, __B),
                                     (__v8si)_mm256_setzero_si256());
}

static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_dpbusds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
{
  return (__m256i)__builtin_ia32_selectd_256(__U,
                                    (__v8si)_mm256_dpbusds_epi32(__S, __A, __B),
                                    (__v8si)__S);
}

static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_dpbusds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
{
  return (__m256i)__builtin_ia32_selectd_256(__U,
                                     (__v8si)_mm256_dpbusds_epi32(__S, __A, __B),
                                     (__v8si)_mm256_setzero_si256());
}

static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_dpwssd_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
{
  return (__m256i)__builtin_ia32_selectd_256(__U,
                                     (__v8si)_mm256_dpwssd_epi32(__S, __A, __B),
                                     (__v8si)__S);
}

static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_dpwssd_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
{
  return (__m256i)__builtin_ia32_selectd_256(__U,
                                     (__v8si)_mm256_dpwssd_epi32(__S, __A, __B),
                                     (__v8si)_mm256_setzero_si256());
}

static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_mask_dpwssds_epi32(__m256i __S, __mmask8 __U, __m256i __A, __m256i __B)
{
  return (__m256i)__builtin_ia32_selectd_256(__U,
                                    (__v8si)_mm256_dpwssds_epi32(__S, __A, __B),
                                    (__v8si)__S);
}

static __inline__ __m256i __DEFAULT_FN_ATTRS256
_mm256_maskz_dpwssds_epi32(__mmask8 __U, __m256i __S, __m256i __A, __m256i __B)
{
  return (__m256i)__builtin_ia32_selectd_256(__U,
                                    (__v8si)_mm256_dpwssds_epi32(__S, __A, __B),
                                    (__v8si)_mm256_setzero_si256());
}

static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_dpbusd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
{
  return (__m128i)__builtin_ia32_selectd_128(__U,
                                        (__v4si)_mm_dpbusd_epi32(__S, __A, __B),
                                        (__v4si)__S);
}

static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_dpbusd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
{
  return (__m128i)__builtin_ia32_selectd_128(__U,
                                        (__v4si)_mm_dpbusd_epi32(__S, __A, __B),
                                        (__v4si)_mm_setzero_si128());
}

static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_dpbusds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
{
  return (__m128i)__builtin_ia32_selectd_128(__U,
                                       (__v4si)_mm_dpbusds_epi32(__S, __A, __B),
                                       (__v4si)__S);
}

static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_dpbusds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
{
  return (__m128i)__builtin_ia32_selectd_128(__U,
                                       (__v4si)_mm_dpbusds_epi32(__S, __A, __B),
                                       (__v4si)_mm_setzero_si128());
}

static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_dpwssd_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
{
  return (__m128i)__builtin_ia32_selectd_128(__U,
                                        (__v4si)_mm_dpwssd_epi32(__S, __A, __B),
                                        (__v4si)__S);
}

static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_dpwssd_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
{
  return (__m128i)__builtin_ia32_selectd_128(__U,
                                        (__v4si)_mm_dpwssd_epi32(__S, __A, __B),
                                        (__v4si)_mm_setzero_si128());
}

static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_mask_dpwssds_epi32(__m128i __S, __mmask8 __U, __m128i __A, __m128i __B)
{
  return (__m128i)__builtin_ia32_selectd_128(__U,
                                       (__v4si)_mm_dpwssds_epi32(__S, __A, __B),
                                       (__v4si)__S);
}

static __inline__ __m128i __DEFAULT_FN_ATTRS128
_mm_maskz_dpwssds_epi32(__mmask8 __U, __m128i __S, __m128i __A, __m128i __B)
{
  return (__m128i)__builtin_ia32_selectd_128(__U,
                                       (__v4si)_mm_dpwssds_epi32(__S, __A, __B),
                                       (__v4si)_mm_setzero_si128());
}

#undef __DEFAULT_FN_ATTRS128
#undef __DEFAULT_FN_ATTRS256

#endif

${this.title}

Code Editor : avx512vlvnniintrin.h